1. Field of the Invention
The present invention generally relates to a conductivity modulation type MOS-FET and particularly relates to a conductivity modulation type vertical MOS-FET.
2. Description of the Prior Art
FIG. 4 shows a cross-section of a main portion of, for example, a general vertical MOS-FET. The main portion is provided with a gate electrode 1, a source electrode 2, a drain electrode 3, and N.sup.- base layer 4, a P.sup.+ layer 5, a P base layer 6, and N.sup.+ drain layer 7, an N.sup.+ source layer 8, a gate polysilicon layer 9, a gate oxidation film 10, and an insulation oxidation film 11. Symbols S, G, and D represent the terminals of the source, the gate, and the drain respectively.
In FIG. 4, if a positive voltage is applied to the gate electrode 1, an inversion layer is formed as a channel for electrons in the surface of the P base layer 6 under the gate polysilicon layer 9, i.e., in the area A shown encircled by a dotted line in the drawing. Therefore, a conductive state is caused between the source electrode 2 and the drain electrode 3. In this case, current components are carried by electrons, and a flow of majority carries of the source electrode 2 or the drain electrode 3 forms a current which is shown as a flow of electrons by an arrow e in FIG. 4. Thus, a general MOS-FET is a mono-polar device in which current components are carried only be electrons or by holes.
On the other hand, FIG. 5 shows a structure of a bi-polar device which is almost the same in structure as the vertical MOS-FET shown in FIG. 4 but in which a larger current can be utilized. In FIG. 5, elements similar to those in FIG. 4 are correspondingly referenced. In FIG. 5, the N.sup.+ drain layer 7 of FIG. 4 is replaced by a P.sup.+ anode layer 12. In this structure, the area A of a P base layer 6 is inverted, and if electrons flow into an N.sup.- base layer 4, holes are injected from the P.sup.+ anode layer 12 into the N.sup.- base layer 4 so that the carrier density in the N.sup.- base layer 4 increases by a large amount. That is, the N.sup.- base layer 4 is subject to conductivity modulation to thereby decrease in resistance so as to have a large current density. In FIG. 5, an arrow h indicates the direction of the hole current.
FIG. 6 illustrates the manufacturing steps for a conductivity modulation type MOS-FET. In the drawings, the P.sup.+ anode layer are not illustrated, and the steps after formation of the anode layer are not illustrated. The steps after formation of the N.sup.- base layer 4 on the P.sup.+ anode layer are shown in order. First, the P.sup.+ layer 5 is formed on the N.sup.- base layer 4, and at the same time the SiO.sub.2 film 13 is partly removed (FIG. 6(b)). Then the SiO.sub.2 gate oxidation film 10 is formed (FIG. 6(c)). Thereafter, the gate polysilicon layer 9 is formed (FIG. 6(d)). Further, a diffusion process is performed to form the P base layer 6 and the N.sup.+ source layer 8 (FIG. 6(e)). The oxidation film 11 is formed (FIG. 6(f)). Finally, the gate electrode 1 and the source electrode 2 of metal such as aluminum are formed (FIG. 6(g)).
The above is a brief description of the structure, operation, and manufacturing steps of a conductivity modulation type MOS-FET as shown in FIG. 5. This device, however, has a defect in that if a very large current is caused to flow through the device, a main current begins to flow through a part of the device other than the area A in the surface of the P base layer 6 so that the gate G cannot control the current any longer. This phenomenon is called "latch-up" and is caused by the structure of the device which forms a PNPN thyristor as shown in FIG. 5.
Referring to the model diagram of FIG. 7, the following is a description of the latch-up phenomenom. In the drawing, the symbol R.sub.N represents a resistance of the N.sup.+ source layer 8, R.sub.p represents a series resistance of the P base layer 6 and the P.sup.+ layer 5, and I.sub.e and I.sub.h respectively represent an electron current and a hole current which flow through the resistances R.sub.N and R.sub.P. Voltage drops across the respective resistance R.sub.N and R.sub.P are expressed as follows on the basis of the source: EQU Due to the electron current: I.sub.e R.sub.N ( 1) EQU Due to the hole current: I.sub.h R.sub.P ( 2)
The junction between the P base layer 6 and the N.sup.+ source layer 8 has a forward bias when the following expression (3) is satisfied: EQU I.sub.e R.sub.N +V.sub.B.ltoreq.I.sub.h R.sub.P ( 3)
where V.sub.B represents a potential difference at the junction between the P base layer 6 and the N.sup.+ source layer 8. At that time, the NPN transistor constituted by the N.sup.30 source layer 8, the P base layer 6, the P.sup.+ layer 5, and the N.sup.- base layer 4 becomes conductive and a number of holes and electrons begin to flow through the junction, so that the device cannot be made non-conductive any longer even if a gate potential is applied which is at an off state because a current is flowing through a part of the device other than the channel. As a result, current continues to flow with ultimate damage to the device. As described above, despite having a capability of making the current density sufficiently large, the conductivity modulation type MOS-FET has a problem in that a large current cannot be utilized in practice due to the latch-up phenomenon. Solution of this problem has been desired.